1. Field of the Invention
The present invention relates to an integrated circuit device with a built-in monolithic temperature sensor. The present invention can be suitably adapted particularly to a semiconductor integrated circuit device having a temperature sensor fabricated in a semiconductor process.
2. Description of the Related Art
Recently, the need for monitoring the operation temperature of an integrated circuit device is growing for the purpose of preventing thermal breakdown of devices in the integrated circuit device and stabilizing the operation of a device having a temperature-dependent characteristic, such as a crystal oscillator, among those devices which are provided in the integrated circuit device.
In this respect, Japanese Patent Laid-Open Publication No. H1-302849, for example, discloses a technique of protecting an LSI (Large Scale Integrated circuit) in a semiconductor integrated-circuit device from thermally broken by a temperature rise by providing a temperature sensor on the same substrate as that of the LSI, deciding that the LSI is abnormally overheated when the temperature detected by the temperature sensor exceeds a predetermined value and then shutting down the LSI.
A technique of using a parasitic pn junction diode as such a temperature sensor is proposed in, for example, Japanese Patent Laid-Open Publication No. H9-229778. FIG. 1 is a cross-sectional view showing a conventional semiconductor integrated circuit device having the temperature sensor described in Japanese Patent Laid-Open Publication No. H9-229778, and FIG. 2 is an equivalent circuit diagram showing the temperature sensor section of the semiconductor integrated circuit device as shown in FIG. 1.
As shown in FIG. 1, this conventional semiconductor integrated circuit device 21 includes a P type silicon substrate PSub and a multi-layer wiring layer M21 formed on the P type silicon substrate PSub. The multi-layer wiring layer M21 is the lamination of plural wiring layers and plural insulating layers alternately laminated. The semiconductor integrated circuit device 21 is provided with a logic circuit section 2, which is formed at the top surface of the P type silicon substrate PSub and a predetermined region of the multi-layer wiring layer M21, and a temperature sensor section 23, which is formed at that region of the top surface of the P type silicon substrate PSub and the multi-layer wiring layer M21 where the logic circuit section 2 is not formed.
A CMOS (Complementary Metal Oxide Semiconductor) circuit 4, for example, is provided in the logic circuit section 2. In the CMOS circuit 4, an N well NW1 and a P well PW1 are formed at the top surface of the P type silicon substrate PSub in such a way as to be adjacent to each other. Two p+ diffusion regions P1 and P2, which becomes a source/drain region, are formed, apart from each other, at the top surface of the N well NW1. Two n+ diffusion regions N1 and N2, which becomes the source/drain region, are formed, apart from each other, at the top surface of the P well PW1. There are a channel region 5 between the p+ diffusion regions P1 and P2 in the N well NW1 and a channel region 6 between the n+ diffusion regions N1 and N2 in the P well PW1.
A gate insulating layer (not shown) is provided at that region in the multi-layer wiring layer M21 which includes regions directly overlying the channel regions 5 and 6, and gate electrodes G1 and G2 of, for example, polysilicon, are respectively provided at the regions directly overlying the channel regions 5 and 6. The gate electrodes G1 and G2 are commonly connected to a gate terminal Vg. The channel region 5, the p+ diffusion regions P1 and P2 as the source/drain region, the gate insulating layer and the gate electrode G1 form a P type MOS transistor. The channel region 6, the n+ diffusion regions N1 and N2 as the source/drain region, the gate insulating layer and the gate electrode G2 form an N-type MOS transistor.
A via V1 is provided on the p+ diffusion region P1 in the multi-layer wiring layer M21 in such a way as to be connected to the p+ diffusion region P1, and a wire W1 is provided on the via V1 in such a way as to be connected to the via V1. A via V2 is provided on the wire W1 in such a way as to be connected to the wire W1, and a power-source potential wire Vcc is provided on the via V2 in such a way as to be connected to the via V2. Accordingly, the p+ diffusion region P1 is connected to the power-source potential wire Vcc through the via V1, the wire W1 and the via V2.
A via V3 is provided on the p+ diffusion region P2 in the multi-layer wiring layer M21 in such a way as to be connected to the p+ diffusion region P2, and a via V4 is provided on the n+ diffusion region N1 in such a way as to be connected to the n+ diffusion region N1. A wire W2 is provided on the vias V3 and V4 in such a way as to be connected to the vias V3 and V4. A via V5 is provided on the wire W2 in such a way as to be connected to the wire W2, and a wire W3 is provided on the via V5 in such a way as to be connected to the via V5. Accordingly, the p+ diffusion region P2 and the n+ diffusion region N1 are connected to the wire W3 through the vias V3 and V4, the wire W2 and the via V5.
Further, a via V6 is provided on the n+ diffusion region N2 in the multi-layer wiring layer M21 in such a way as to be connected to the n+ diffusion region N2, and a wire W4 is provided on the via V6 in such a way as to be connected to the via V6. A via V7 is provided on the wire W4 in such a way as to be connected to the wire W4, and a ground potential wire GND is provided on the via V7 in such a way as to be connected to the via V7. Accordingly, the n+ diffusion region N2 is connected to the ground potential wire GND through the via V6, the wire W4 and the via V7.
A p+ diffusion region P3 is formed at that region of the top surface of the P type silicon substrate PSub which is other than the region where the N well NW1 and the P well PW1 are formed. A via V8, a wire W5, a via V9 and a ground potential wire GND are provided on the p+ diffusion region P3 in the multi-layer wiring layer M21 in order in the bottom-to-top direction, and the p+ diffusion region P3 is connected to the ground potential wire GND through the via V8, the wire W5 and the via V9.
In the temperature sensor section 23, an N well NW2 is formed at the top surface of the P type silicon substrate PSub, and a p+ diffusion region P21 and an n+ diffusion region N21 are formed apart from each other at the top surface of the N well NW2. A via V21, a wire W21, a via V22 and a ground potential wire GND are provided on the p+ diffusion region P21 in the multi-layer wiring layer M21 in order in the bottom-to-top direction, and the p+ diffusion region P21 is connected to the ground potential wire GND through the via V21, the wire W21 and the via V22.
A via V23 is provided on the n+ diffusion region N21 in the multi-layer wiring layer M21 in such a way as to be connected to the n+ diffusion region N21, and a wire W22 is provided on the via V23. The wire W22 is connected to the via V23 at one end, and is connected to an output terminal Vout 21. A via V24 is provided under the wire W22 in such a way as to be connected to the other end of the wire W22, and a resistor R of, for example, polysilicon is provided under the via V24. The resistor R has a sheet shape whose one end is connected to the via V24. The resistor R is formed at the same time as the gate electrodes G1 and G2 of the CMOS circuit 4 and is provided at the same level as the gate electrodes G1 and G2. A via V25 is provided on the resistor R in such a way as to be connected to the other end of the resistor R. A wire W23, a via V26 and a power-source potential wire Vcc are provided on the via V25 in order in the bottom-to-top direction, and the resistor R is connected to the power-source potential wire Vcc through the via V25, the wire W23 and the via V26.
Accordingly, a potential higher than the potential to be applied to the p+ diffusion region P21 is applied to the N well NW2. Consequently, forward pn junction is formed between the p+ diffusion region P21 and the N well NW2, thereby forming a parasitic pn junction diode D.
In the multi-layer wiring layer M21, the vias V1, V3, V4, V6, V8, V21 and V23 are provided in a first insulating layer in which the gate electrodes G1 and G2 and the resistor R are provided in the same level. The wires W1, W2, W4, W5, W21, W22 and W23 are provided in the same level in a first wiring layer provided on the first insulating level, and the vias V2, V5, V7, V9, V22 and V26 are provided in a second insulating layer provided on the first wiring layer. Further, the individual ground potential wires GND, the individual power-source potential wires Vcc, and the wire W3 are provided in the same level in a second wiring layer provided on the second insulating layer. Those portions of the multi-layer wiring layer M21 which exclude the individual vias, the individual wires and the resistor R, and the layer overlying the second wiring layer are buried with an insulation material 7.
In the temperature sensor section 23 of the semiconductor integrated circuit device 21, as shown in FIG. 2, the resistor R and the parasitic pn junction diode D are connected in series in this order from the power-source potential wire Vcc toward the ground potential wire GND, and the output terminal Vout 21 is connected to the node between the resistor R and the parasitic pn junction diode D. The parasitic pn junction diode D is connected in the forward direction.
With the structure, as shown in FIG. 1, when the temperature of the semiconductor integrated circuit device 21 changes, the characteristic of the parasitic pn junction diode D changes, which changes the potential of the output terminal Vout 21. The temperature of the semiconductor integrated circuit device 21 can be measured by detecting the potential of the output terminal Vout 21. Because the parasitic pn junction diode D can be formed in the semiconductor integrated circuit device 21 by using the device structure of an MOS transistor, the temperature sensor section 23 can be formed without changing the conventional MOS process.
The prior art however has the following problem. According to the prior art shown in FIGS. 1 and 2, as the temperature coefficient of the parasitic pn junction diode D is as low as 0.002/K or so, a sufficient SNR (Signal-to-Noise Ratio) cannot be acquired.